Modern microprocessors have a large number of clock domains in order to be able to achieve the best performance for targeted applications while optimizing for overall chip power consumption. In order to facilitate deterministic data transfer across these clock domains the clocks are typically aligned using a state-machine controlled digital delay-locked loop (DLL). Typically these clocks are at the end of long insertion delay distribution networks and hence susceptible to supply-noise induced jitter. When this jitter becomes comparable to the unit increment of the delay line, it can cause the state machine to falsely align the clock to the incorrect edge of the reference clock.